1. Field of the Invention
The present invention relates to a method for manufacturing complementary insulated gate field effect transistors (hereinafter referred to as CMIS FET's) having a field oxide layer of LOCOS (local oxidation of silicon) structure, and more particularly to a method for manufacturing a semiconductor integrated circuit device comprising such transistors.
2. Description of the Prior Art
In prior art CMIS FET's of the LOCOS structure, a power supply voltage therefor is determined by a threshold voltage V.sub.th of an active region which is a channel region immediately beneath a gate electrode and a threshold voltage V.sub.th of a parastic MOS FET in a field oxide layer region. Accordingly, when it is desired to raise the power supply voltage for the CMIS FET's, it is necessary to change the impurity concentration of a substrate and the impurity concentration of a well layer which is of opposite conductivity type to that of the substrate. Namely, the threshold voltage V.sub.th is defined by ##EQU1## WHERE Q.sub.b is a charge in a bulk, Q.sub.ss is surface state and oxide charge, and C.sub.g is the capacitance of the gate. A simple way to control the threshold voltage V.sub.th defined by the equation (1) is to control Q.sub.b. That is, Q.sub.b is related to the impurity concentration of the substrate and it increases as the impurity concentration of the substrate increases. Accordingly, V.sub.th can be increased by increasing the impurity concentration of the substrate.
Thus, when it is desired to raise the operation voltage, a voltage applied to a wiring layer extending over the field oxidation region also rises, resulting in a parastic channel immediately beneath the field oxide layer region. That is, a parastic MOS FET is formed. In order to avoid the formation of such a parastic MOS FET, it is necessary to increase the impurity concentration of the substrate or the impurity concentration of the well layer as seen from the above equation to raise the threshold voltage V.sub.th of the parastic MOS FET. However, since the impurity concentrations of the substrate and the well layer are determined by electrical characteristics of the CMIS FET's such as the threshold voltage V.sub.th and mutual conductance gm, the range of the operating voltage for the CMIS FET's is limited and the magnitude thereof is very small. For example, when the threshold voltage V.sub.th of an N-channel MOS FET formed in a P-type well layer is 0.45 volts, a parastic channel is formed at about 4 volts because an N-type inversion layer is readily formed because of many sodium (+) ions present in the field oxide layer. As a result, the operating voltage should be up to about 3 volts.
As a commonly used method for manufacturing the CMIS FET's of the LOCOS structure which avoids the formation of the parastic channel in the P-type well layer and which can be practiced in a simple way, a technique disclosed in the Philips Technical Review, Vol. 34, No. 1, 1974, pp. 19-23, is known. According to the technique disclosed therein, particularly in the right column on page 20 and FIG. 2 on page 21, the P-type well layer is formed by ion implantation technology after the formation of the LOCOS oxide (field oxide) layer. Therefore, while the parastic channel is not readily formed, a complex design of layout for the MOS FET's and the wiring layers therefor is required when a plurality of MOS FET's are to be incorporated in the P-type well layer because LOCOS oxides cannot be formed in the P-type well layer. The operating voltage is also limited. That is, according to the disclosed technique, the operating supply voltage should be up to about 10 volts because as the operating voltage rises, the area immediately beneath the LOCOS oxide formed in the semiconductor body is more apt to form a parastic channel by a wiring layer extending over the LOCOS oxide layer although the above area is made more N-type conductive by sodium (+) ions present in the LOCOS oxide. Furthermore, due to the threshold voltage V.sub.th of the active region in the P-type well layer, it becomes impossible to prevent the formation of the parastic channel in the P-type well as the operating voltage rises. Accordingly, the field of application of the semiconductor integrated circuit device manufactured by the disclosed technique is limited.
On the other hand, the field of application of the semiconductor integrated circuit device comprising CMIS FET's is wide in these days and, actually, the operating voltage therefor varies widely depending on the specification of a particular product. It is, therefor, required to manufacture CMIS FET's applicable to a variety of products of various specifications in a common process and provide CMIS FET's which are satisfactorily operable with a wide range of operating voltages. To this end, a method for manufacturing CMIS FET's which can control the threshold voltage V.sub.th of the active region of the CMIS FET's and the threshold voltage V.sub.th of the parastic MOS FET to predetermined voltages is required.